We Don't Predict Latency.
We Schedule Through It.
Time-Based Scheduling is a fundamentally different architecture: it hides memory latency by knowing exactly when results will arrive, enabling sustained execution without speculation-driven stalls.
The scheduler knows. The pipeline never waits.
Conventional out-of-order processors speculate about when data will arrive and recover when they're wrong. TBS takes a different approach — at instruction issue time, the processor knows exactly when each result will be available, and schedules accordingly.
Designed to reduce dependence on branch misprediction recovery and reduce pipeline flushes — sustaining throughput where conventional designs stall.
Instruction timing is determined at issue — no runtime speculation or recovery needed.
Execution determinism by design.
| Execution determinism | Full / by design |
| Branch prediction | Not required |
| Speculation overhead | Zero |
| Vector extension | RVV 1.0 |
| VLEN range | 128 – 2048 bits |
| Data path | 2× VLEN |
| Peak performance | 2.56 TOPS (5nm, single core) |
No wall between CPU and VPU.
The gap doesn't close. The processor stops caring.
At 10-cycle memory latency, SimplEx is 2.8× faster than best-in-class RISC-V CPU/VPU. At 100-cycle DRAM latency — real-world edge conditions — the advantage grows to 16×. SimplEx performance stays flat across the entire range.
No preload. No DMA. No dedicated SRAM.
Non-cacheable memory latency is the silent killer in embedded AI. SimplEx's predictive load mechanism delivers data on schedule — eliminating stalls before they occur, not recovering from them after.
The only architecture with Data Path = 2× VLEN.
RISC-V VPU offers a meaningful efficiency advantage over SIMD-only designs. SimplEx extends this with a 2× VLEN data-path and flexible chaining — a 2× TOPS boost over standard vector architectures.
| Architecture | Type | VLEN Range | Data Path | Chaining | 2× VLEN |
|---|---|---|---|---|---|
| ARM Neon (Cortex-A78) | SIMD | 128-bit fixed | 128-bit | ✗ | ✗ |
| ARM SVE2 (Neoverse) | SIMD+ | 128–2048-bit | = VLEN | ✗ | ✗ |
| Cadence DNA 100 | RISC-V Vector | 1024–4096-bit | = VLEN | ✓ | ✗ |
| SiFive X390 | RISC-V Vector | 512-bit | = VLEN | ✓ | ✗ |
| SimplEx Micro | Double Flex Chain | 128–2048-bit | 2× VLEN | ✓✓ | ✓ |
Time-Based Microprocessors
In this white paper, Founder & CTO Dr. Thang Tran details a novel time-based architecture that achieves high-performance execution without the overhead of traditional dynamic schedulers.
7 pages · PDF
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See the architecture validated.
RTL-validated performance. Measured, not estimated.
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