AI silicon is fast.
It just isn't busy.
Memory makes it wait.
We don't.
A differentiated architecture designed to sustain throughput under memory latency. We license RTL processor IP to SoC design teams.
We sell IP.
Not chips.
Our customers ship their best product spec — longest battery life, lowest system cost — because our core delivers roughly 12x the performance per watt of the next-best RISC-V vector core at realistic memory latency.
SimplEx Micro licenses our synthesizable soft-core processor IP platform to SoC design teams. One RTL, twenty configurations. You integrate our Time-Based Scheduling core into your chip. We supply the RTL, simulation models, compiler support, and integration documentation.
The gap is widening, not closing.
AI is moving into cars, drones, robots, and factories — where decisions must happen locally, instantly.
In real-time systems, peak TOPS mean nothing if performance collapses under memory latency.
CPU + NPU/GPU designs are not adaptable to constantly evolving workloads.
Billions of dollars of RISC-V investment makes custom, latency-tolerant processors viable now.
Physical AI will be won by architectures that control latency — not chips that only advertise peak performance.
AI Has Become Memory Bound.
Compute continues to scale. Memory latency has become the limiting factor. More FLOPS no longer guarantee more performance.
Memory is roughly one hundred times slower than the processor it feeds.
The industry has spent four decades working around the gap — not closing it.
Fast silicon spends much of its time waiting on data it cannot get any sooner.
We Don't Predict Latency.
We Schedule Through It.
Time-Based Scheduling is a fundamentally different architecture: it hides memory latency by knowing exactly when results will arrive, enabling sustained execution without speculation-driven stalls.
See How TBS Works →Designed to reduce dependence on branch misprediction recovery.
The vector unit is part of the core — no slow handoff to a separate chip.
The 100-cycle DRAM gap is still there. The processor simply doesn't stall.
No GPU, TPU or NPU to partition work across, and no hops between blocks.
Performance under real DRAM latency.
Faster at low latency (10 cycles) vs. best-in-class RISC-V CPU/VPU
Faster at high latency (100 cycles) — where competitors stall
SimplEx performance from 10 → 100 cycles of latency
Performance stays high when memory gets slow. Exactly what matters at the edge.
Benchmark: MatMul FP16 latency sweep · SimplEx vs. best-in-class RISC-V CPU/VPU. Measured on RTL.
From validated architecture to licensed IP.
Now, soon, later.
- 4-wide RTL complete
- Performance model released and correlated to RTL
- FPGA prototype in progress
- Silicon Catalyst portfolio company
- Configurable variants — one RTL, twenty configurations
- Verification and software stack
- Customer integration
- Automotive and humanoid robotics applications
- Tape-out