In AI, Memory Is the Wall.
SimplEx Is the Breakthrough.
A differentiated architecture designed to sustain throughput under memory latency. We license RTL processor IP to SoC design teams.
We sell IP.
Not chips.
Simplex Micro licenses RTL processor IP to SoC design teams. You integrate our Time-Based Scheduling core into your chip. We supply the RTL, simulation models, compiler support, and integration documentation.
No chip. No fab. No supply chain.
The gap is widening, not closing.
AI is moving into cars, drones, robots, and factories — where decisions must happen locally, instantly.
In real-time systems, peak TOPS mean nothing if performance collapses under memory latency.
CPU + NPU/GPU designs are not adaptable to constantly evolving workloads.
Billions of dollars of RISC-V investment makes custom, latency-tolerant processors viable now.
Physical AI will be won by architectures that control latency — not chips that only advertise peak performance.
AI Has Become Memory Bound.
Compute continues to scale. Memory latency has become the limiting factor. More FLOPS no longer guarantee more performance.
Memory is roughly one hundred times slower than the processor it feeds.
The industry has spent four decades working around the gap — not closing it.
Time-Based Scheduling is the first architecture engineered for real memory conditions.
We Don't Predict Latency.
We Schedule Through It.
Time-Based Scheduling is a fundamentally different architecture: it hides memory latency by knowing exactly when results will arrive, enabling sustained execution without speculation-driven stalls.
See How TBS Works →Designed to reduce dependence on branch misprediction recovery.
The vector unit is part of the core — no slow handoff to a separate chip.
The 100-cycle DRAM gap is still there. The processor simply doesn't stall.
Performance highlights.
Matrix multiply, measured on RTL
Peak, single core @ 5nm
64-core system, modeled
Speculative execution overhead