The performance model continues to move forward with support from CircuitSutra.

On the front end, the branch prediction unit model is now in place, and test cases are being developed and run using instruction streams from the ISS. The focus is on validating branch behavior in more detail, including working through specific examples to confirm how the global history register and global history table should operate and updating the model based on those results.

On the execution side, more instruction types are now running through the model. ALU, multiply, and store instructions have been exercised through the pipeline. During this process, issues in the instruction pipeline were identified and corrected, including conflicts in the time-resource model and cases where instructions were not stalling correctly. These updates improve the accuracy of instruction timing and flow.

Integration with the vector side is also progressing. The VPU C++ interface model is now working with the existing VPU model, and VPU test cases are starting to run. In parallel, we are defining how VPU activity will be represented in the graphical model so that scalar and vector execution can be observed together.

Figure 1: Cycle-by-cycle pipeline view from the performance model showing instruction issue, execution, and write-back across time

The visualization effort continues to support this work. Pipeline and IPC outputs are being prepared for use in external presentations, helping to make system behavior more visible and easier to understand.

This was a shorter reporting period, but a longer working session. Much of the time was spent working through detailed examples to clarify branch prediction behavior and ensure the model reflects it correctly.

The model is now handling a broader set of instructions, and the interaction between the front end, execution model, and vector processing is becoming more realistic. Next steps are to expand instruction coverage, continue refining branch behavior, and improve integration between scalar and vector execution.

By: Thang Tran, CEO/CTO Simplex Micro