By: Thang Tran, CTO Simplex Micro

Two-week report. Good progress.

The performance model is moving forward with CircuitSutra. Benchmarks are a couple of weeks out. No L2 cache yet. I expect to start correlating against RTL in about a month—at that point RTL will need to catch up to the model, not the other way around.

On the vector side, we ran floating-point vector instructions on the VPU model. Most are working. Four FP instructions are not yet implemented. The model is behaving correctly and is close to complete.

On the CPU front end, all blocks in the branch prediction unit are implemented. Basic blocks are extracted from the ISS, simulation is running, and instruction flow is now entering the system.

On the execution side, the basic time-resource performance model is done. The performance model TRM is based on the RTL TRM but encompasses all possible resources in the processor for execution of all instructions including the load and store instructions. Work has started on statistics collection and sensitivity data for performance analysis.

We are not at full end-to-end execution yet. The front-end validates the branch prediction and fetching instruction in accordance to the ISS. Independently, the back-end executes instructions from the ISS output. 

The pipeline graph is working and showing around 40 cycles. The output looks right. Next is making the cycle count configurable and allowing the window to shift.

The model is coming together. VPU mostly working. Front end running. Execution model processing instructions. Visualization active.

Next: expand coverage, improve statistics, start running real benchmarks. After that, correlation with RTL—measuring how close the model is to hardware.