The performance model has reached an important inflection point. The major components are now in place, and the system is ready to begin running code.

On the front end, the branch prediction and instruction fetch models are complete, with test cases validating behavior. Early assumptions around instruction cache timing and branch handling have been corrected, resulting in a more accurate and stable baseline.

The backend is now fully implemented. The pipeline is handling instruction flow with corrected timing behavior, including updates to load miss handling, CSR access, and several execution edge cases. These changes improve how instructions move through the system and retire.

The cache models are now integrated, completing the core system.

Vector integration has also crossed a key threshold. The VPU interface model is complete, and vector execution is now active in the system. Minor issues with VPU instruction latency are being aligned through ongoing validation.

With the structure complete, the team is beginning to run real workloads. The first phase uses Dhrystone compiled with RVV disabled to establish CPU correlation with RTL before enabling vector execution in the next phase.

The model will generate statistical data such as IPC, cache hit/miss rates, and branch misprediction behavior. The focus now shifts to validation, correlation, and measurement.

By Thang Tran, CTO, Simplex Micro