Every development program has a turning point where the question shifts from “does it work?” to “can we prove it?” We’ve reached that point. After achieving RTL completion, and performance modeling, the focus has moved from construction to validation. It means we’re no longer asking whether the architecture is sound. We’re demonstrating it quantitatively.

CircuitSutra team is wrapping up TinyML, which transitions it from an active workload to a completed, validated benchmark. The relevant instruction types, branch mispredictions, and cache misses are added to the IPC graphs to provide more useful information for customer. Those visualizations will make a real difference to see exactly why performance changes.

After Dhrystone and TinyML, the next benchmark is Matmul, matrix multiplication. Matrix multiplication underlies transformers, CNNs, GEMM kernels, and essentially every modern AI workload of consequence. Correlating Matmul well strengthens confidence in every AI benchmark that follows.

The CircuitSutra team is extending the VPU memory model to 100-cycle latency. One of SimplEx’s fundamental claims is that performance remains nearly constant as memory latency increases. We’re now pushing the model into exactly that regime to verify it.

The most encouraging number in this update: we’re closing in on the Qwen performance discrepancy, targeting within 5%. If the performance model tracks RTL within 5% on a transformer inference workload, it becomes a credible instrument for predicting silicon performance before tape-out. That’s not a minor milestone. It’s the foundation for every benchmark claim we’ll make going forward.

The roadmap is expanding. Stage 2 begins in July and will add L2 cache modeling, sensitivity analysis, realistic queue sizing, and wrong-path execution estimation. That moves well beyond basic processor timing into modeling production-quality CPU behavior. We’re no longer building. We’re proving. And the numbers are starting to speak for themselves.

By Thang Tran, CTO, SimplEx Micro