See the architecture in motion.
Video walkthroughs of Time-Based Scheduling, RTL results, and the team behind the architecture.
Conversation with the CTO: RISC-V, Meta MTIA, and the Vector Engine Built Before the Spec Existed
Host Jonah McLeod sits down with SimplEx Micro founder and CTO Dr. Thang Tran to trace the RISC-V vector engine Thang architected at Andes — now shipping inside Meta's MTIA silicon — built before the RISC-V Vector ISA was even finalized.
Conversation with the CTO Episode 6
Dr. Thang Tran goes deep on how the performance model actually works, including its foundational advantage over RTL — perfect visibility into every instruction's execution.
Conversation with the CTO Episode 5
Part of the Conversations with the CTO series with founder and CTO Dr. Thang Tran.
CircuitSutra Demo 1
A companion walkthrough to Episode 5. Dr. Thang Tran looks at recent improvements to the performance model's IPC Viewer — the tool included in every performance model package.
PM Visualizer
A look at the SimplEx performance model's visualizer tool.
2 Minute PM-Visualizer
Paul walks through setting up and using the performance model's visualizer: run the CircuitSutra Linux package, generate CSV trace and log output, then read the results.
Episode 4
Part of the Conversations with the CTO series with founder and CTO Dr. Thang Tran.
Conversation with the CTO (Part 2)
Thang Tran discusses a major milestone — Dhrystone, Matrix Multiply, TinyML, and Qwen now run successfully to completion on the performance model.
New Video: Conversation with the CTO
Thang Tran walks through the architectural decisions, modeling approach, and hardware tradeoffs behind SimplEx Micro's RISC-V RVA23 performance model.