Every performance claim traces back to RTL.
Not a spreadsheet model.
IPC within 5% of RTL.
Correlated cycle-by-cycle, pipeline-stage by pipeline-stage using Dhrystone (CPU) and Matrix Multiplication (VPU). Branch prediction and cache hit rates match RTL at 100%.
IPC correlation tolerance vs. RTL
Branch prediction match vs. RTL
Cache hit rate match vs. RTL
Configurable from the model.
I-cache and D-cache: 16KB – 128KB
L2 cache: 512KB – 4MB
Memory latency: 10 – 128 cycles
Vector register width (VLEN): 128 – 2048 bits
GCC RISC-V compiler · Whisper ISS · Cycle-accurate model
Benchmark suite: Dhrystone · MatMul · Qwen · YOLO
Instruction manual — run it yourself
Cycle-accurate. Stage by stage.
IPC within 5% of RTL — correlated cycle-by-cycle, pipeline-stage by pipeline-stage using Dhrystone (CPU) and Matrix Multiplication (VPU).
Qwen 2.5 7B — verified on the model.
Qwen 2.5 7B · FP16 · batch 1 · 100-cycle DRAM penalty
17 SpecInt2k6/GHz (8-wide) or 14 SpecInt2k6/GHz (4-wide) running concurrently with Qwen — with reduced resource conflict due to TBS scheduling.
CircuitSutra partnership.
Performance modeling is conducted in partnership with CircuitSutra for independent TBS performance correlation. UCI compiler development is ongoing alongside RTL verification.
Granted and filed patents.
Microprocessor Patents
| Patent # | Title | Grant Date |
|---|---|---|
| US-11829187-B2 | Microprocessor with Time Counter for Statically Dispatching Instructions | 11/28/2023 |
| US-11829767-B2 | Register Scoreboard for a Microprocessor with a Time Counter | 11/28/2023 |
| US-11829762-B2 | Time-Resource Matrix for a Microprocessor with Time Counter | 11/28/2023 |
| US-12190116-B2 | A Microprocessor with Apparatus and Method for Replaying Instructions | 1/7/2025 |
| US-12169716-B2 | Microprocessor with a Time Counter for Statically Dispatching Extended Instructions | 12/17/2024 |
Vector Processor Patents
| Patent # | Title | Grant Date |
|---|---|---|
| US-12106114-B2 | Microprocessor with Shared Read and Write Buses and Instruction Issuance to Multiple Register Sets | 10/1/2024 |
| US-12112172-B2 | Vector Microprocessor with a Time Counter for Statically Dispatching Instructions | 10/8/2024 |
| US-12124849-B2 | Vector Microprocessor with Extended Vector Register Sets | 10/22/2024 |
| US-12288065-B2 | Microprocessor with Odd and Even Registers | 4/29/2025 |
| US-12282772-B2 | Vector Microprocessor with Vector Data Buffer | 4/22/2025 |
Additional applications filed and pending. Full list available on request.